Addressing Clock Tree Synthesis Challenges
In order to equalize the clock delay to all clock inputs, the Clock Tree Synthesis (CTS) approach involves the automatic insertion of buffers and inverters along the clock channels of the ASIC design. CTS is used to minimize insertion latency and balance clock skew.
What are the CTS goals?
CTC goals are,#
- Minimize clock skew.
- Minimize power dissipation.
- Minimize the insertion delay.
What are the i/p required for CTS?
Following i/p required for CTS#
- NDR rules.
- Clock tree DRCs.
- Detailed placement database.
- The target for latency and skew if specified.
- Buffers or inverters to build the clock tree.
What are the effects of CTS?
Here are the effects of CTS#
- Clock buffers are added
- Congestion may increase
- Non-clock cells may have been moved to the less ideal location.
- It can introduce timing and max transition/capacitance violations.
Why should we solve setup violations before CTS and hold violations after CTS?
Hold violations and setup violations are both dependent on the clock path. The CTS clock path was initially assumed to be ideal because we lacked the clock path’s skew and transition numbers, however, this knowledge is adequate to carry out setup analysis. Hold violations are corrected after CTS because the clock has been spread.
What is CTO (Clock Tree Optimization)?
Clock Tree Optimization improves the clock skew and clock insertion delay by applying additional optimization. CTO is performed during the clock_opt process.
