Why is a P-type (100) substrate doped with boron preferred?

P-type (100) Substrate

CMOS integrated circuits start with a P-type (100) substrate heavily doped with boron to minimize substrate resistivity and enhance latch-up immunity[1]. This helps in reducing substrate debiasing, crucial for avoiding CMOS latch-up. The substrate choice is a preventative measure against latch-up, a phenomenon where parasitic structures cause unintended current paths.

Significance of Epitaxial Growth

The initial step involves epitaxial growth, adding a lightly doped P-type epitaxial layer (epi) on the substrate. This thin layer, 5 to 10μm thick, serves as the back gate for NMOS transistors. Unlike standard bipolar processes, CMOS processes do not require buried layers, allowing the use of epi-coated wafers that can be stockpiled for various products. Although epitaxy increases costs, it improves latch-up immunity by enabling the use of a P+ substrate and offers better control over MOS transistor parameters.

What are the steps involving N-well diffusion?

The next step is N-well diffusion, where after thermal oxidation, a patterned photoresist with the N-well mask is used. Ion implantation through oxide windows creates a deep lightly doped N-type region, the N-well. In an N-well CMOS process, NMOS transistors are in the epi, and PMOS transistors reside in the N-well. This process optimizes NMOS transistor performance, slightly degrading PMOS transistor performance due to increased total dopant concentration in the well.

There’s also mention of the P-well CMOS process, where NMOS transistors are in the N-epi, and PMOS transistors are in a P-well. This process optimizes PMOS transistor performance but may face challenges with biasing an N-type substrate in designs with multiple power supplies. The N-well process, chosen for illustration, provides slightly better NMOS transistor performance, a grounded substrate, and compatibility with BiCMOS technology.