How to Become an Analog Layout Engineer
Analog layout design is a discipline that deals with the physical implementation of schematic blocks to the chip top level. The field of Analog Layout Design focuses on the chip layout design for a particular Analog and digital mixed-signal design. In analog design, the layout guys work at the transistor level. They work on smaller blocks. The analog design consists of R, C and MOSFETs, and BJTs.
Analog Layout Designers should have an understanding of routing processes and physical verification checks like Layout versus Schematics (LVS). They need knowledge of Analog circuits (Bandgap, LDO, Opamp, PLL, and Standard cells. Understanding of Design Rule Checking (DRC). Dealing with deep sub-micron process matters like Lachup, Antenna, EM, IR, Tapeout.
Becoming an Analog Layout Engineer requires a combination of education, skills, and experience. Here are the steps you can follow to become an Analog Layout Engineer
Layout versus Schematics (LVS)
- Shorts: identifies overlapping wires that are not supposed to be connected
- Opens: Incomplete connection for certain nets
- Property mismatch: identifies mismatches in parameter
- The number of spaces between metal layers
- The minimum width rule
- The via rules etc.
Electrical Rule Checking (ERC)
Duties of an Analog Layout Design Engineer
Analog Layout Design Engineers are responsible for creating layouts for analog and mixed-signal ICs, optimizing the layout for performance and reliability, conducting layout verification, collaborating with cross-functional teams, staying up-to-date with industry advancements, and managing project timelines.
Important Tools for Analog Layout Design
Custom Compiler: providing design entry, simulation management and analysis, and custom layout editing features
PrimeSim SPICE: a multi-core/multi-machine simulator that is well-suited for the simulation of large, complex analog and RF circuits
IC Validator: a comprehensive and high-performance signoff physical verification solution that improves productivity for customers at all process nodes
PrimeSim HSPICE: the gold standard for accurate on-chip simulation and silicon-to-package-to-board-to-backplane signal integrity simulation and analysis
StarRC: the gold standard for parasitic extraction
