What are DRC & how will you fix them? DRC stands for “design rule check.” In the context of integrated…
Author: siliconvlsi
What is CMP (chemical mechanical polishing)? Chemical mechanical polishing/planarization (CMP) is a process that removes materials by a combination of…
What is the Contact Spike phenomenon in VLSI? Contact spike is a phenomenon that can occur in very large-scale integration…
Best Practice for Analog Layout Design Here are some best practices for analog layout design: Start with a good floorplan:…
NWELL Antenna Effect The NWELL antenna effect is a phenomenon that can occur in CMOS (Complementary metal-oxide-semiconductor) circuits when the NWELL…
Fin Field-Effect Transistor FinFET (Fin Field-Effect Transistor) is a type of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) that uses a thin, vertical…
Why do we use p substrate in CMOS? Starting with a p-type substrate allows one to build n-channel transistors without…
What are Resistance Capacitance and Inductance? Resistance Capacitance and Inductance are primary components of an Electric circuit. Resistance All materials…
Triple-Well Processes Triple-Well Processes are used to isolate the most sensitive circuit in Analog Layout Design. A triple-well structure contains…
CMOS Process Integration: FEOL & BEOL The CMOS process integration is often divided into two major parts: the front end…