Following is the input for Physical design.
- Basic ASIC flow
- Basic Verilog concepts
- Understanding of the synthesis process
- Scripting languages like PERL and TCL
- Basic understanding of DFT(Design for testability)
- Cadence database format, ICC2 NDM format, and ICC Milkyway structure
- STA knowledge. I strongly recommend the STA book, nanometer by Bhaskar
- Sanity checks like check design and check timing.
- Congestion and how to solve it in floorplan and placement stage
- Tool’s behavior for placing standard cells and routing
- Tool commands, reporting, and skills of scripting as per requirements
- Floorplan objects like macro, special cells like decap, endcap, tie, tap cells
- Linux command prompt, shell scripting, VIM editor skills, file handling operations
- Physical libraries, LEF(Library Exchange Format), DEF Design Exchange Format
- CTS(Clock tree synthesis) inputs and parameter checking and control like skew and latencyTool knowledge of Synthesis, PnR, and STA tools. Once these are cleared, one can focus on other sign-off tools
- Understanding of inputs to physical design like the structure of timing libraries, contents of tech file, tlu+, SDC(Synopsys design constraints),
