Close Menu
  • Analog Design
    • Latest Analog Layout Interview Questions (2025)
  • Digital Design
    • Digital Electronics Interview Question(2025)
    • Top VLSI Interview Questions
  • Physical Design
    • Physical Design Interview Questions for VLSI Engineers
  • Verilog
    • Verilog Interview Questions(2024)
  • Forum
Facebook Instagram YouTube LinkedIn WhatsApp
SiliconvlsiSiliconvlsi
Ask Questions Register in Forum Login in Forum
Facebook Instagram YouTube LinkedIn WhatsApp
  • Analog Design
    • Latest Analog Layout Interview Questions (2025)
  • Digital Design
    • Digital Electronics Interview Question(2025)
    • Top VLSI Interview Questions
  • Physical Design
    • Physical Design Interview Questions for VLSI Engineers
  • Verilog
    • Verilog Interview Questions(2024)
  • Forum
SiliconvlsiSiliconvlsi
VLSI Design

Strings in Tcl

By siliconvlsiOctober 7, 20220

Strings in Tcl A string is a sequence of characters. Unlike other languages, Tcl does not usually require double quotes…

Digital Design

Metastability in VLSI Circuits: Effects on Design Reliability

By siliconvlsiOctober 5, 20220

Metastability The designed circuit can get into states where the signals can settle to an intermediate value between logic 0…

Digital Design

Double Patterning in Lithography: Techniques and Applications

By siliconvlsiOctober 5, 20220

Double Patterning To get better resolution and get higher density, double patterning is used. For the following nodes, only the…

Physical Design

Worst and Best Timing Path

By siliconvlsiOctober 5, 20220

Worst and Best Timing Path The path which is having the largest delay is known as the worst path, late…

Physical Design

Time Borrowing Concept

By siliconvlsiOctober 5, 20220

What is Time Borrowing Concept? A shorter path can borrow time from the following path of later logic using the…

Physical Design

What do you mean by critical path, false path, and multicycle path?

By siliconvlsiOctober 5, 20220

Critical path, false path, and multicycle path Critical path The critical path is considered that timing-sensitive to the functional path…

Physical Design

What are the main reasons for setup or hold time violations?

By siliconvlsiOctober 5, 20220

What are the main reasons for setup or hold time violations? Main reasons for setup or hold time violations Design…

Physical Design

What do you mean by Launch and capture edge?

By siliconvlsiOctober 5, 20220

What do you mean by Launch and capture edge?  The launch edge is the active edge of the clock at…

Memory Layout Design

SRAM Memory Architecture

By siliconvlsiOctober 2, 20220

Static random-access memory In SRAM memory, a single cell stores 1 bit of data. This data bit is represented by…

VLSI Design

Why PMOS pass strong 1 and weak 0

By siliconvlsiOctober 2, 20220

Why PMOS pass strong 1 and weak 0 The current equation for PMOS is the following, for PMOS to turn…

Load More
Facebook X (Twitter) Instagram Pinterest Vimeo YouTube
  • About Us
  • Contact Us
  • Privacy Policy
© 2026 Siliconvlsi.

Type above and press Enter to search. Press Esc to cancel.