What is Power Planning?
One of the most important stages in physical design is power planning. It will be utilized to supply power to macros and standard cells while staying under the IR-Drop limit. The resistance of the metal wires that make up the power distribution network causes a steady-state IR Drop. Steady-state IR Drop minimizes the voltage differential between local power and ground, lowering the speed and noise immunity of local cells and macros.
- Rings: Its Carries VDD and VSS around the chip
- Stripes: Its Carries VDD and VSS from Rings across the chip
- Rails: It connects VDD and VSS to the standard cell VDD and VSS.
- Trunk: The connection between Pad and Ring
- Pad: Interface from IC to the outside world.
Power planning involves following things
- Calculating the required number of power pins
- Rings and stripes count
- Ring and striped widths
- IR drop
Why do we do a power plan before the placement of standard cells in Physical design?
Before determining the ideal site for a cell, Place and Route tools will do timing and congestion analyses. If the PG mesh is not present during the placement task, the congestion estimate will be incorrect. That is, even if the placement concludes that there is no congestion. If you want to draw power mesh later, you might not be able to find enough tracks.
So it is always best practice in today’s designs to do all PG routing before starting PnR. It will reduce preroute- post-route correlation issues and provide predictable results.
What is VerifyPowerVia/Missing Via/Enough Via check in VLSI?
This checks for any via missing intersection points between the layers, if any via is missing then we need to add vias again or in that specific location, we need to add power via separately. In some companies have this script that will fill automatic vias(Auto Via Check). Make sure there are no routing blockages or any other nets in that region.
Floorplanning and Powerplannig are necessary for Physical design
|Analog and Memory Layout Design Forum|
|Physical Layout Desing Forum|
|RTL & Verilog Design Forum|
|Analog Layout Design Interview Questions||Memory Design Interview Questions|
|Physical Design Interview Questions||Verilog Interview Questions|
|Digital Design Interview Questions||STA Interview Questions|