Power Reduction Techniques in VLSI
The sum of the total current fed into the circuit and the total voltage drop, or leak current, is known as power dissipation. Power dissipation is an inescapable limitation on a device’s portability.
To tackle these issues, various traditional techniques are used, such as clock gating, power gating, variable frequency, variable voltage supply, and variable device threshold. Additionally, modern techniques like dynamic power reduction, leakage power reduction, and back biasing are also employed. These approaches aim to reduce power consumption and enhance the overall efficiency of the devices.
Types of Power Dissipation
The circuits experience different types of power dissipation, which can be categorized as follows:
Static power dissipation
When the system is not powered or in standby mode, power dissipation occurs in the form of leakage current. Several sources of leakage current exist in circuits, such as subthreshold leakage, diode leakages around transistors and n-wells, tunnel currents, gate leakage, etc.
Dynamic power dissipation
Logic transitions in the circuits cause logic gates to charge and discharge load capacitance. In other words, this type of power dissipation occurs due to the switching activities of transistors.
Power considerations in SOC (System on Chip) are driven by several factors:
- Environmental concerns.
- Battery life.
- Digital noise immunity.
- Packaging cost.
- Cooling cost.
The principles of low-power designs are as follows
- Utilizing higher frequency devices and using them at the lowest possible frequency.
- Disconnecting the power supply when the system is not in use.
- Controlling power dissipation at the architectural level.
- Implementing pipelining and parallelism to operate at the lowest required frequency.
- Using the lowest possible supply voltage.
Power Reduction Techniques in CMOS
| Traditional Techniques |
Dynamic Power Reduction | Leakage Power Reduction | Other Power Reduction |
|---|---|---|---|
| Clock gating | Implement clock gating | Minimize usage of VT cells | Minimize oxide devices |
| Variable frequency | Use variable frequency | Back biasing | Power-efficient circuit |
| Variable voltage supply | Utilize variable voltage supply | Reduce oxide thickness | – |
| Variable device threshold | Set variable device threshold | Variable island | Use FET |