Leakage Current in CMOS

Leakage Current in CMOS: 7 Powerful Ways to Reduce Power Loss

Leakage current in CMOS refers to the unwanted current that flows through a transistor or circuit even when the transistor is intended to be in the OFF state.

Ideally, a CMOS transistor should consume very little power when it is not switching. However, practical MOSFETs always have small unwanted current components caused by physical mechanisms such as weak inversion, reverse-biased junctions, gate tunneling, and high electric fields near the drain.

As semiconductor technology scales to smaller dimensions, leakage becomes increasingly important because it can contribute significantly to the total power consumption of modern integrated circuits.

Understanding the different leakage mechanisms is therefore essential for VLSI design, low-power design, CMOS technology, and semiconductor device engineering.

What Is Leakage Current in CMOS?

Leakage current is the unintended current that flows through a MOS transistor when it is supposed to be turned OFF.

For an ideal MOSFET, the OFF-state current would be zero. In a real device, however, several physical mechanisms allow a small amount of current to flow.

The total OFF-state current can contain contributions from different sources, including:

• Subthreshold leakage
• Reverse-biased source/drain junction leakage
• Gate direct-tunneling leakage
• Gate-induced drain leakage (GIDL)

These mechanisms have different physical origins and become important under different operating conditions.

Why Is CMOS Leakage Current Important?

Leakage current has become an important concern as transistor dimensions have continued to shrink.

A single transistor may have only a very small leakage current, but a modern integrated circuit can contain millions or billions of transistors.

Even a small leakage component per transistor can therefore result in significant total standby power.

High leakage can cause:

• Increased standby power
• Higher chip temperature
• Reduced battery life
• Increased cooling requirements
• Lower energy efficiency
• Reliability concerns
• Difficulty meeting low-power design targets

This is particularly important in battery-powered systems and high-density semiconductor devices.

Four Major Types of Leakage Current

There are four commonly discussed leakage mechanisms in CMOS transistors:

1. Subthreshold leakage
2. Reverse-biased source/drain junction leakage
3. Gate direct-tunneling leakage
4. Gate-induced drain leakage (GIDL)

Each mechanism is described below.

1. Subthreshold Leakage

Subthreshold leakage occurs when a MOS transistor operates below its threshold voltage.

When the gate-to-source voltage is below the threshold voltage, the transistor is normally considered to be OFF.

However, the channel is not completely free of carriers.

A small amount of current can still flow between the source and drain because of carrier diffusion in the weak-inversion region.

This current is known as subthreshold current or weak-inversion current.

Why Does Subthreshold Leakage Occur?

When:

VGS < VTH

the MOSFET is below its conventional turn-on condition.

However, the carrier concentration in the channel does not suddenly become zero at the threshold voltage.

Instead, it decreases gradually as the gate voltage is reduced.

As a result, a small drain current continues to flow.

This current is strongly dependent on the threshold voltage.

A lower threshold voltage generally results in a higher OFF-state current.

Therefore, low-VT devices are usually faster but can have greater standby leakage than high-VT devices.

Factors Affecting Subthreshold Leakage

Subthreshold current depends on several parameters, including:

• Threshold voltage
• Temperature
• Gate voltage
• Drain voltage
• Channel length
• Body voltage
• Process technology

Temperature is particularly important because leakage generally increases as temperature rises.

This creates an important relationship between power and temperature in modern chips.

2. Reverse-Biased Source/Drain Junction Leakage

Another important leakage mechanism occurs at the reverse-biased junctions between the source/drain regions and the semiconductor body.

Consider an NMOS transistor.

The source and drain are formed using n-type regions inside a p-type body.

These regions form p-n junctions with the surrounding semiconductor.

When the transistor is OFF, these junctions can be reverse biased depending on the applied voltages.

Even under reverse bias, a small current can flow through the junction.

Components of Junction Leakage

Reverse-biased junction leakage can contain different physical components.

These include:

• Generation of electron-hole pairs in the depletion region
• Carrier diffusion and drift near the depletion-region boundaries
• Tunneling-related components in highly doped or strongly biased structures

The magnitude depends on factors such as:

• Junction area
• Junction perimeter
• Doping concentration
• Temperature
• Reverse-bias voltage
• Semiconductor process

As technology changes, the relative importance of different junction leakage mechanisms can also change.

3. Gate Direct-Tunneling Leakage

Gate direct-tunneling leakage is associated with the very thin dielectric separating the gate electrode from the semiconductor channel.

In a MOS transistor, the gate dielectric acts as an insulating barrier.

Ideally, it prevents current from flowing directly between the gate and the semiconductor.

However, when the dielectric becomes extremely thin, quantum-mechanical tunneling can allow carriers to pass through the barrier.

This produces gate leakage current.

Why Does Gate Tunneling Increase?

As the gate dielectric becomes thinner, the tunneling probability increases significantly.

The gate electric field can also become large, further influencing the tunneling mechanism.

Several tunneling mechanisms may be considered, including:

• Electron conduction-band tunneling
• Electron valence-band tunneling
• Hole valence-band tunneling

The dominant mechanism depends on the device structure, dielectric material, voltage conditions, and process technology.

High-k Dielectrics and Gate Leakage

Modern CMOS technologies introduced high-k dielectric materials to reduce gate leakage while maintaining strong gate control.

A high-k dielectric can provide a larger physical thickness for a similar electrical oxide thickness.

This helps reduce direct tunneling through the dielectric while maintaining the required gate capacitance.

Therefore, advanced transistor technologies use dielectric engineering as one approach to controlling gate leakage.

4. Gate-Induced Drain Leakage (GIDL)

Gate-induced drain leakage, commonly called GIDL, is another important OFF-state leakage mechanism.

GIDL is associated with a strong electric field near the drain region, particularly when the gate voltage is low while the drain voltage is relatively high.

For example, consider an NMOS transistor with:

• Gate connected to ground
• Drain connected to a positive supply
• Source at a low potential

Under these conditions, a strong electric field can develop near the gate-drain region.

The resulting electric field can cause significant band bending in the semiconductor.

How Does GIDL Occur?

The strong electric field near the drain can promote carrier generation through mechanisms such as:

• Band-to-band tunneling
• Impact-ionization-related effects under suitable conditions

The generated carriers can contribute to current flowing from the drain toward the body or other terminals.

The resulting current is commonly referred to as GIDL.

GIDL can become more important as devices are scaled and electric fields become stronger.

Leakage Current Comparison

The four major leakage mechanisms can be summarized as follows:

The relative contribution of each mechanism depends on the transistor technology and operating conditions.

How Does Threshold Voltage Affect Leakage?

Threshold voltage is one of the most important parameters affecting OFF-state leakage.

A transistor with a lower threshold voltage can switch faster because it requires less gate voltage to establish strong channel conduction.

However, the same lower threshold voltage generally produces greater subthreshold current when the device is supposed to be OFF.

This creates a fundamental trade-off:

Lower VTH → Higher speed + Higher leakage

Higher VTH → Lower leakage + Lower speed

This is one reason modern standard-cell libraries commonly provide multiple threshold-voltage options.

LVT, SVT, and HVT Cells

Many standard-cell libraries provide different threshold-voltage variants.

Common examples include:

• LVT — Low Threshold Voltage
• SVT — Standard Threshold Voltage
• HVT — High Threshold Voltage

LVT cells are generally used on timing-critical paths where performance is important.

HVT cells are useful where leakage reduction is more important than maximum speed.

SVT cells provide a balance between the two.

This approach is commonly called multi-Vt optimization.

For example:

Critical timing path → LVT

Normal path → SVT

Non-critical path → HVT

This allows designers to balance performance and leakage at the circuit level.

Why Does Leakage Increase With Temperature?

Temperature has a strong influence on several leakage mechanisms.

As temperature increases, carrier-related processes become more significant.

For example, subthreshold leakage generally increases with temperature.

This can create a feedback effect:

Higher leakage → Higher power → Higher temperature → More leakage

This behavior is particularly important in high-density integrated circuits.

Thermal management and power optimization therefore need to be considered together.

How Can Leakage Current Be Reduced?

Reducing leakage requires a combination of transistor-level, circuit-level, and physical-design techniques.

Some commonly used approaches include:

1. Use Higher Threshold Voltage Devices

HVT cells generally have lower leakage than LVT cells.

Designers can therefore replace non-critical LVT cells with HVT or SVT cells where timing allows.

This reduces standby power without unnecessarily slowing the entire design.

2. Use Multi-Vt Optimization

Using only one threshold-voltage option across an entire chip is often inefficient.

Instead, different cell types can be selected according to timing requirements.

For example:

• Critical paths → LVT
• Moderate paths → SVT
• Non-critical paths → HVT

This provides a practical balance between performance and power.

3. Power Gating

Power gating disconnects selected blocks from the power supply or ground during periods when they are not required.

Special high-threshold-voltage sleep transistors can be used to reduce leakage from inactive blocks.

This technique is widely used in low-power digital design.

4. Transistor Sizing

Transistor dimensions influence leakage, capacitance, drive strength, and delay.

Reducing unnecessary transistor width can reduce some leakage components and capacitance.

However, transistor sizing must be performed carefully because reducing device size can also affect timing and signal integrity.

5. Body Biasing

Body biasing changes the voltage between the transistor body and source.

Depending on the process and circuit architecture, body biasing can be used to modify threshold voltage.

For example, reverse body bias can increase the effective threshold voltage and reduce subthreshold leakage.

Forward body bias can improve performance but may increase leakage.

6. Supply Voltage Optimization

Reducing the supply voltage can reduce several power components.

However, lowering supply voltage also affects:

• Performance
• Noise margins
• Signal integrity
• Timing
• Circuit reliability

Therefore, supply voltage optimization must be considered together with performance requirements.

7. Optimize the Process and Device Structure

At the technology level, semiconductor manufacturers can use techniques such as:

• High-k gate dielectrics
• Improved channel engineering
• Optimized junction structures
• Halo or pocket implants
• Advanced transistor architectures
• Improved isolation structures

These techniques help control different leakage mechanisms at the device level.

Leakage Power vs Dynamic Power

It is important to distinguish leakage power from dynamic power.

Dynamic Power

Dynamic power is primarily associated with charging and discharging capacitances when signals switch.

A simplified expression is:

Pdynamic ≈ α × C × V² × f

where:

• α = switching activity
• C = capacitance
• V = supply voltage
• f = operating frequency

Leakage Power

Leakage power exists even when the circuit is not actively switching.

It can be approximated as:

Pleakage = Ileakage × VDD

where:

• Ileakage = total leakage current
• VDD = supply voltage

Therefore, leakage power becomes particularly important in circuits that spend significant amounts of time in standby.

Why Is Leakage a Bigger Problem in Modern CMOS?

Technology scaling has provided major improvements in transistor density and performance.

However, smaller devices also introduce challenges such as:

• Lower threshold voltages
• Stronger electric fields
• Thinner gate dielectrics
• Shorter channel lengths
• Increased sensitivity to process variations

These effects can increase certain leakage mechanisms.

As a result, modern VLSI design must consider leakage from the beginning of the design process rather than treating it as an issue only at the end.

Leakage Current in CMOS and Low-Power VLSI

Low-power VLSI design focuses on reducing both dynamic and static power.

Leakage becomes especially important in applications such as:

• Smartphones
• Wearable devices
• IoT systems
• Battery-powered sensors
• Mobile processors
• Memory circuits
• Always-on systems

For these applications, the circuit may remain powered for long periods even when little computational activity is taking place.

Reducing OFF-state current can therefore significantly improve energy efficiency and battery life.

Common Questions About Leakage Current in CMOS

What is leakage current in CMOS?

Leakage current is the unwanted current that flows through a CMOS transistor or circuit when the transistor is intended to be OFF.

What are the four major types of CMOS leakage?

The four commonly discussed types are subthreshold leakage, reverse-biased source/drain junction leakage, gate direct-tunneling leakage, and gate-induced drain leakage.

Which leakage mechanism is caused by operation below threshold voltage?

Subthreshold leakage occurs when the gate-to-source voltage is below the transistor’s threshold voltage and a small current continues to flow through the weak-inversion region.

Why does LVT have higher leakage?

LVT devices have a lower threshold voltage. This improves switching performance but generally increases the OFF-state subthreshold current.

What is GIDL?

GIDL stands for Gate-Induced Drain Leakage. It occurs near the drain under conditions that produce a strong electric field, particularly when the gate voltage is low and the drain voltage is relatively high.

What causes gate leakage?

Gate leakage can occur because carriers tunnel through a very thin gate dielectric. The probability of tunneling increases as the dielectric becomes thinner.

How can CMOS leakage be reduced?

Common approaches include using HVT cells, multi-Vt optimization, power gating, body biasing, transistor sizing, supply-voltage optimization, and device-level process improvements.

Does leakage current increase with temperature?

Generally, several leakage mechanisms, particularly subthreshold leakage, increase significantly with temperature.

Why is leakage important in low-power design?

Leakage consumes power even when the circuit is not switching. This makes it particularly important for battery-powered and always-on systems.

Key Takeaways

Leakage current in CMOS is an unavoidable consequence of the physical behavior of real MOS transistors.

The most important points are:

• Leakage current flows even when a transistor is intended to be OFF.
• Subthreshold leakage is associated with weak inversion below the threshold voltage.
• Junction leakage occurs through reverse-biased source/drain junctions.
• Gate tunneling is associated with carrier tunneling through a thin dielectric.
• GIDL is associated with strong electric fields near the drain.
• Lower-VT devices generally provide better performance but higher leakage.
• HVT devices can reduce leakage on non-critical paths.
• Multi-Vt optimization helps balance speed and standby power.
• Power gating can significantly reduce leakage from inactive blocks.
• Temperature can strongly influence leakage.
• Modern low-power designs must consider leakage at multiple levels, from transistor technology to physical implementation.

In simple terms:

CMOS power consumption = Dynamic power + Leakage power

Understanding the different leakage mechanisms is therefore essential for designing efficient, reliable, and low-power VLSI circuits.