What is Metastability in VLSI and How to Avoid it?
A race condition in the circuit’s input signals is typically the cause of metastability in VLSI (very large-scale integration), which is the phenomenon where a digital circuit may momentarily enter an undetermined state.
Reasons for Metastability in VLSI
In VLSI circuits, metastability can happen for a number of reasons:
- Noise
- Low VDD.
- Cross talk.
- Device aging
- High clock skew
- Process variation
- Temperature variations
- High parasitic capacitances.
- Excessive combinational delay
- If the input is an asynchronous signal
How metastability can be avoided or tolerated in a circuit.
The issue of metastability can be to some extent mitigated if input data adhere to setup and hold time limitations. Controlling metastability is challenging if the signals come from many clock domains.
- Use asynchronous reset.
- Provide the needed settling time.
- Use metastable hardened flip-flops.
- The clock period should be precise to avoid delay.
- Use the metastability filter, but it will increase slack.
- Add one or more successive synchronizing flip-flops to the synchronizer.
