Design for Testability (DFT) is an effective approach to address challenges related to power consumption and large data volumes in the testing process after production, particularly in designs using lower geometry nodes. DFT plays a vital role in saving costs, reducing power consumption, decreasing testing time, minimizing chip area, managing pin counts, and handling new fault types during the testing phase itself.
Reduced Pin Count Testing (RPCT)
As semiconductor designs become more complex with the demand for lower geometries like 28nm, 16nm, 7nm, and beyond, the number of I/O pins on processors continues to increase. This exponential growth in transistor count impacts the cost of enhancing testers and the application of test patterns, requiring multiple test cycles for achieving high test quality. To address these challenges efficiently and reduce overall product costs, DFT engineers are adopting new testability techniques such as reduced pin-count testing (RPCT).
Reduced pin-count testing is an effective solution that allows the application of at-speed test patterns using low-cost testers with limited pins. This technique enables improvements in coverage, reduces implementation testing time, and has minimal impact on the design.
The Use of DFT Scan Insertion and Compression Techniques to Handle DRC Violations
Compression techniques in DFT are used to optimize tester application timing and data volume area. Scan insertion and compression techniques are applied in the DFT methodology to achieve high-quality testability for IC (SoC/ASIC) designs at a low cost.
As the development of lower geometry designs leads to increased power density and heat dissipation, which can reduce reliability and damage ICs, DFT engineers employ clock gating, voltage shut-offs, and other methods during functional mode operations to manage power and heat dissipation issues. DFT scan insertion and compression techniques are proposed to handle Design Rule Check (DRC) violations while managing controllability and observability in the functional mode.
Low Power Design and Management Techniques in DFT
As chip size continues to shrink, low-power design becomes a critical issue that needs to be addressed concurrently with design for testability during functional operations. DFT and lower power design challenges are closely related. DFT is applied to power management circuitries using a power test access mechanism to improve power dissipation during Automatic Test Pattern Generation (ATPG).
Power Domain Connected with Functional Blocks: The device includes multiple functional blocks that can be independently powered up or down by controlling power switches connected to each block for power supply.
Multiple Supply Voltages through Level Shifters: Power domains are connected through level shifters on signals transitioning from one voltage level to another based on functional operation phase conditions. Level shifters ensure proper sampling of voltage supply values, enabling correct operation when integrating functional blocks with different voltage supplies on a system-on-chip.
Isolation Logic Cells: DFT isolates floating values that occur when power is gated off to prevent incorrect values within the power domain. Isolation logic cells act as buffers, providing constant Logic 0 (ISO 0) or Logic 1 (ISO 1) values to power blocks.
Retention Cells: Retention cells, such as state retention power gating (SRPG) cells, are used to retain the state of the power domain before it is shut off. This helps in saving leakage power during shutdown and ensures proper power-up recovery.
Clock Gating: Clock gating is a technique employed to reduce power dissipation in the power-on domain by dynamically blocking clock pulses to a set of chip elements. This technique improves power usage efficiency and flexibility during functional operations.
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