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Home»VLSI Design»Stress-Induced Voiding in Interconnects
VLSI Design

Stress-Induced Voiding in Interconnects

siliconvlsiBy siliconvlsiJuly 22, 2023Updated:July 28, 2024No Comments1 Min Read
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Understanding Stress-Induced Voiding in Metal Conductors

Stress-induced voiding (SIV), or stress migration, happens when metal conductor ions move due to high tensile stresses in the interconnect after certain processing steps, like passivation deposition. This migration leads to the formation of voids within the metal conductor. The root cause of these stresses is the difference in thermal expansion between the metal layer and the underlying Si-substrate, as well as between the metal and the passivation layer or intermetal dielectric.

Stress-Induced Voiding (SIV)
Stress-Induced Voiding (SIV)

Impact on ULSI Chips

The effects of SIV can be detrimental to the performance and reliability of Ultra-Large Scale Integration (ULSI) chips. Some of the consequences include:

  • Changes in resistance
  • Formation of voids that can lead to open circuits
  • Growth of hillocks (protrusions)
  • Development of whiskers (thin filaments) that may cause shorts between lines or layers

Importance of Managing SIV

These issues significantly impact the electrical properties of ULSI chips, especially with the use of advanced copper metallization. Managing stress-induced voiding is crucial for ensuring the reliability and functionality of integrated circuits, making it an important consideration during the design and manufacturing processes.

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