Close Menu
Ask Questions Register in Forum Login in Forum

Forum

siliconvlsiBy Updated:No Comments1 Min Read
Select category
What is the difference between the normal buffer and the clock buffer?
AnsweredDigitalWorld answered 2 weeks ago • 
136 views3 answers0 votes
What is the difference between OASIS and GDS?
Answeredsemiconductor answered 1 month ago • 
292 views3 answers0 votes
Why might deep N-well isolation fail in preventing latch-up in a multi-domain analog layout?
AnsweredCircuitCreator answered 1 month ago • 
218 views3 answers0 votes
Why is using dummy poly in some standard cell rows considered harmful in FinFET nodes?
AnsweredDigitalWorld answered 2 months ago
208 views2 answers0 votes
How can you minimize mismatch in a large array of current mirrors distributed across a chip?
AnsweredDigitalWorld answered 2 months ago • 
227 views3 answers0 votes
How do you preserve symmetry in a differential layout when routing metal with strict layer usage constraints?
AnsweredChipWhiz answered 2 months ago • 
220 views3 answers0 votes
What layout technique would you apply to reduce substrate noise coupling in a densely packed mixed-signal block?
AnsweredDigitalWorld answered 2 months ago • 
172 views2 answers0 votes
Why would we prefer an active inductor over a passive inductor in RF integrated circuit design?
AnsweredLogicNode answered 2 months ago • 
153 views1 answers0 votes
What is the difference between PODE and CPODE?
AnsweredChipWhiz answered 2 months ago • 
548 views2 answers1 votes
Why we are using blockage Layers in Analog Layout?
AnsweredLogicNode answered 2 months ago • 
163 views1 answers0 votes
What are Through-Silicon Vias (TSVs)?
AnsweredChipWhiz answered 2 months ago
224 views2 answers0 votes
Why circuit people don’t design layout also in the VLSI domain?
AnsweredDigitalDecode answered 2 months ago • 
350 views3 answers0 votes
Layout – How well tap cells reduce latch up in std cell layout
AnsweredAnalogIP answered 2 months ago • 
290 views3 answers0 votes
How do I design a low-pass or high-pass filter?
AnsweredAnalogIP answered 2 months ago • 
275 views1 answers0 votes
TX(transmitter) and Rx(Receiver) are there in LPDDR, so why do we place TX near to ESD device? why not RX?
AnsweredSemiCustom answered 2 months ago • 
294 views2 answers0 votes
What is PLL in Analog Design?
AnsweredLogicNode answered 2 months ago
217 views1 answers0 votes
How do you optimize the common centroid layout for a differential pair when dealing with multi-finger Transistors?
AnsweredAnalogIP answered 3 months ago • 
389 views2 answers0 votes
What are the best Interconnect trategies in VLSI Layout design?
AnsweredSemiCustom answered 6 months ago • 
413 views3 answers0 votes
What is Overdrive Voltage in Transistors?
Opensiliconvlsi asked 6 months ago
231 views0 answers0 votes
How do low-Vt and high-Vt devices differ specifically in their fabrication processes?
Opensiliconvlsi asked 6 months ago • 
30 views0 answers0 votes
Ask Question