How can you minimize mismatch in a large array of current mirrors distributed across a chip?

I think layout matching is super important here. We always use common-centroid layout for current mirrors, especially when they’re spread out. It helps cancel out gradients across the chip. You also want to keep the same orientation and make sure the devices are as identical as possible. It’s a bit of extra effort, but it really cuts down mismatch.

In our team, we focus more on using dummy devices around the mirrors. They help to keep the environment of each device similar. We’ve seen that when you skip the dummies, edge effects cause more mismatch. So even in a large array, if you wrap everything properly, the results are way more consistent.

I believe the best way is to avoid spreading them too far in the first place. If you can cluster the current mirrors closer together, it’s easier to control temperature and voltage variations. We also use matched routing for the control lines. So I’d say keep things tight and balanced wherever possible.