What happens if setup time is violated but hold time is satisfied in a flip-flop?

From my experience, when you violate setup time, you sometimes see metastability. That means the output of the flip-flop is not a clean 0 or 1, but it stays unstable for some time. Even though hold time is satisfied, you still can’t trust the output in this case.

If setup time is violated but hold time is okay, I think the data might not be captured correctly. The flip-flop may latch the wrong value because the input didn’t arrive early enough before the clock edge. In real circuits, this usually means timing failure.