Since their introduction at 14 nm, FinFETs have been the workhorse technology for five generations. As foundry offerings, we’ve seen it at 14nm, 10nm, 7nm, and 5nm. At 22nm, Intel did introduce finFETs. At least for TSMC, 3nm will also be a finFET node. The usual cell libraries must be scaled if you require logic scaling.
The active device width that is available to manufacture the finFET is decreasing as you scale the typical cell library from a 7.5-track to a 6-track or a 5-track. As a result, the fin configuration changes from three fins at 7.5-track to two fins at 6-track to one fin at 5-track. Devices with a single fin are more varied. One of the causes of finFETs ceasing to scale is this.
3nm appears to be the last node for finFETs.
This equation, known as chip scaling, is valid as long as the market is able to produce new, faster transistors that use the same amount of power, or less at roughly the same cost per chip. Vendors have started shipping finFET-based devices since 2011. These are the most recent generation of transistors.
But as finFETs rapidly reach their limits, a new technology at the 3nm and/or 2nm manufacturing nodes will be required. Performance requirements, process technologies, and design guidelines are referred to as nodes in a technological generation. In a fab, process technology is a recipe utilized to make a chip. Beyond 2nm nodes are now known as Angstrom nodes in the silicon industry.