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  • Analog Design
    • Latest Analog Layout Interview Questions (2025)
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    • Physical Design Interview Questions for VLSI Engineers
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Digital Design

Understanding minority charge injection

By siliconvlsiMarch 21, 20220

Understanding minority charge injection A p-n junction diode is a two-terminal or two-electrode semiconductor device, which allows the electric current in…

VLSI Design

Temperature Inversion (Impact on Performance)

By siliconvlsiMarch 21, 20220

Temperature Inversion in VLSI There In a lower technology node, as temperature increases the threshold voltage decreases so overdrive voltage…

VLSI Design

What is HVT, SVT(RVT) & LVT cells?

By siliconvlsiMarch 16, 20220

What is HVT, SVT(RVT) & LVT cells? The threshold voltage, Vt of a cell depends on the channel doping of…

Digital Design

Why do we use filler cells in VLSI?

By siliconvlsiMarch 16, 20220

 What is a filler cell? Filler cells primarily are non-functional cells used to continue the VDD and VSS rails. Filler…

Digital Design

Standard Cell Library for ASIC Design

By siliconvlsiMarch 16, 20220

 Standard Cell Library for ASIC Design Standard cells are designed based on power, area, and performance(PPA), which is used in…

Digital Design

Difference between Analog and Digital layout

By siliconvlsiMarch 16, 20220

Difference between Analog and Digital layout Analog Layout needs matching while digital layout doesn’t need matching Analog layout needs guarding…

Analog Design

Latest Analog Layout Interview Questions (2025)

By siliconvlsiMarch 16, 20220

Latest Analog Layout Interview Questions (2025) Interviews provide an opportunity to showcase your skills and demonstrate your suitability for the…

Analog Design

NMOS and PMOS Transistors- Analog design

By siliconvlsiMarch 15, 20220

NMOS and PMOS Models There are two types of MOSFETs: NMOS and PMOS.  NMOS uses N-type doped semiconductors as the…

Analog Design

Analog Layout Design-Improve Parasitic Capacitance in IC layouts

By siliconvlsiMarch 14, 20220

Parasitic Capacitance in IC Layouts Parasitics can be of resistance or capacitance types, or both. As the semiconductor industry is…

Analog Design

Why bias voltage for PMOSFETs are referred to shield with VDD? Why not VSS?

By siliconvlsiMarch 12, 20220

To understand these let’s take the example of PMOS’s current source. The drain current of the source depends on the…

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