Deep Sub-Micron (DSM) refers to very tiny sizes in chip technology, smaller than 0.18µm. It’s a part of the scaling down of VLSI technology, following Moore’s Law, where chip components like width, length, and thin oxide layers are reduced. Other factors like supply voltage and densities also play a role. Different techniques are used for scaling, including Constant Field Scaling and Constant Voltage methods.
DSM Effects in VLSI
- Interconnect Delay: As chips get smaller, wire delays become more important than gate delays.
- Crosstalk Noise and Delay Unpredictability: Signals can interfere with each other, making timing predictions hard.
- Reliability: Issues like Electro Migration and Current Density become more critical.
- Power Consumption: Smaller chips can consume more power due to increased capacitance.
What is Interconnect Delay?
Let’s assume, that in a 0.5µm technology, a 1mm metal wire may have a delay of 15ps, but in a 0.1µm technology, the delay could be 340ps due to wire resistance. Solutions include slowing down height scaling and using better conductors like copper.
Comparison of Solutions
Copper has lower resistivity than aluminum and is more resistant to electro-migration. Using materials with lower dielectric constants can also help reduce capacitance.
What is Crosstalk Noise in VLSI?
High aspect ratio lines can increase coupling capacitance, affecting signal integrity. Accurate design rules and redesigning techniques are necessary to mitigate this.
Power
Dynamic power increases with smaller sizes and higher frequencies. Scaling down voltage helps reduce dynamic power. Static power also increases with smaller sizes, but multi-technology approaches can manage this.
Conclusion
DSM presents challenges like delay, power consumption, and crosstalk. Solutions involve using new materials, design rules, and careful redesigning. These solutions are implemented before or during chip manufacturing.