What is HVT, SVT(RVT) & LVT cells? The threshold voltage, Vt of a cell depends on the channel doping of…
Browsing: VLSI Design
ls command The ls command is used to view the contents of a directory. There are variations you can use with…
Fabrication Processes There are serval steps that include in the Fabrication Process. Oxidation Oxidation is a process that converts silicon…
ESD in VLSI ESD occurs when two bodies at different potentials come in direct contact or if there is a…
What is EPI in Silicon VLSI Technology? EPI stands for Epitaxial Silicon layer. The EPI layer is doped appropriately for…
What is latchup in CMOS and its prevention Techniques “Latch-up is the state where a semiconductor undergoes a high-current state…
New Technologies in VLSI (2024) The transistor density of chips keeps going up as the process node goes down, and…
Gate-Induced Drain Leakage – An Overview GIDL(Gate Induced Drain Leakage) occurs where the gate partially overlaps with the drain of…
Polysilicon used as a gate contact instead of metal in CMOS The polysilicon gate acts as a mask for the…
Drain Induced Barrier Lowering (DIBL) Drain Induced Barrier Lowering (DIBL) is a short channel effect in MOSFET prominent in ultra-scaled…